This application claims the priority benefit of Taiwan application serial no. 88108048, filed May 18, 1999, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
This invention relates to integrated circuit (IC) technology, and more particularly, to a multi-stage polydiode-based electrostatic discharge (ESD) protection circuit for use in an IC device to protect the internal circuit of the IC device against ESD.
2. Description of Related Art
The CMOS (Complementary Metal-Oxide Semiconductor) technology an advanced IC fabrication technology that combines both N-type and P-type MOS transistors on the same substrate to form logic gates or memory cells. However, CMOS-based IC devices are particularly susceptible to electrostatic discharge (ESD). When ESD occurs, the resulted ESD voltage would be typically greater than the system voltage used to drive the IC device, and therefore can easily break through the gate oxide layer in the CMOS structure, causing damage to the internal circuit of the IC device. To cope with ESD, CMOS-based IC devices are commonly provided with an ESD protection circuit to allow the IC device to be immune to ESD.
Polydiode is a semiconductor component now widely used in CMOS technology for the fabrication of many kinds of ICs, such as IC cards and smart cards. The polydiode is typically utilized as a rectifying element in bridge rectifying circuitry. However, since polydiode is typically unconnected to the IC substrate, it would be incapable of diverting ESD current, when it occurs, to the substrate. In terms of ESD protection, the polydiode can only provide a very limited capability. This is because that the polydiode would be nearly incapable of providing a protection capability above 1 KV (kilovolt) due to its inherent electrical characteristics, which makes it unsuitable for Human-Body Model (HBM) ESD protection and, needless to say, Machine Model (MM) and Charge-Device Model (CDM) protection.
Presently, polydiode-based IC devices are provided with only one stage of polydiode circuitry prior to the connection to the gate. This design scheme would offer only a very limited level of ESD protection. At the 2 xcexcm level of fabrication process or above, it can provide a 750 V level of HBM ESD protection. However, at the submicron level of fabrication process or below, the HBM ESD protection would be reduced to only between 100 V to 500 V, which would make the IC device highly susceptible to ESD.
It is therefore an objective of this invention to provide a multi-stage polydiode-based ESD protection circuit, which can help improve the switching speed of the polydiode through the use of a finger-type polydiode so that ESD current can be more quickly drained away.
It is another objective of this invention to provide a multi-stage polydiode-based ESD protection circuit, which can help increase the ESD protection capability in submicron IC devices.
It is still another objective of this invention to provide a multi-stage polydiode-based ESD protection circuit, which can help provide adequate ESD protection against various types of ESD, including HBM, MM, and CDM.
In accordance with the foregoing and other objectives of this invention, a novel multi-stage polydiode-based ESD protection circuit is provided.
Broadly speaking, the invention is embodied as a multi-stage polydiode-based ESD protection circuit. In one preferred embodiment, the multi-stage polydiode-based ESD protection circuit is embodied as a 2-stage circuit.
In use, the multi-stage polydiode-based ESD protection circuit is provided between a bonding pad and the internal circuit of an IC device for the purpose of protecting the internal circuit of the IC device against any ESD voltage applied to the bonding pad. The multi-stage polydiode-based ESD protection circuit of the invention comprises: (a) a plurality of stages of polydiode circuits, each stage including a first polydiode and a second polydiode, the first polydiode having a positive end connected to a connecting node and a negative end connected to a first system voltage, and the second polydiode having a positive end connected to a second system breakdown voltage lower in level than the first system voltage and a negative end connected to the connecting node, with the connecting node in the first stage of polydiode circuit being connected to the bonding pad and the connecting node in the last stage of polydiode circuit being connected to the internal circuit of the IC device; (b) a plurality of resistors, each being used to connect one stage of polydiode circuit to the next stage of polydiode circuit in such a manner as to be connected between the connecting node of one stage of polydiode circuit and the connecting node of the next stage of polydiode circuit; and (c) a power protection circuit, connected between the first system voltage line and the second system voltage line, for draining ESD current on the first system voltage line to the second system voltage line.
When embodied as a 2-stage polydiode-based ESD protection circuit, it comprises: (a) a first stage of polydiode circuit including a first polydiode and a second polydiode, the first polydiode having a positive end connected to a first node connected to the bonding pad and a negative end connected to a first system voltage, and the second polydiode having a positive end connected to a second system breakdown voltage lower in level than the first system voltage and a negative end connected to the first node; (b) a resistor having a first end connected to the first node and a second end connected to a second node; (c) a second stage of polydiode circuit including a first polydiode and a second polydiode, the first polydiode having a positive end connected to the second node and a negative end connected to the first system voltage, and the second polydiode having a positive end connected to the second system voltage and a negative end connected to the second node; and (d) a power protection circuit, connected between the first system voltage line and the second system voltage line, for draining ESD current on the first system voltage line to the second system voltage line.